Electronic calculator chip having test input and output

ABSTRACT

An MOS/LSI semiconductor chip for providing the functions of an electronic calculator includes a data memory, an arithmetic unit for executing operations on data from the memory, and a control arrangement for defining the functioning of the machine including a ROM for storing a large number of instruction words, an instruction register for receiving instruction words from the ROM and reading out parts to various sections of the control arrangement, and an address register for selecting the location in the ROM for read out of the next instruction. Input and output terminals are provided for keyboard input, display output, timing signals, etc. A test mode of operation is provided for quality control upon completion of manufacture of the chip. The test mode allows the entire ROM to be tested by reading in addresses to the address register from external and reading out the resulting word from the instruction register. During the test mode, normal incrementing and branching of the address register may be externally inhibited.

United States Patent 11 1 Bryant et al.

[ Nov. 18, 1975 ELECTRONIC CALCULATOR CHIP Primary Examiner-Gareth D. Shaw HAVING TEST INPUT AND OUTPUT Assistant Examiner-John P. Vandenburg Attorney, Agent, or Firm-Har0ld Levine; Edward .I. [75] Inventors: John D. Bryant, Houston; Glenn A. Connors, J J h 1 Graham Hartsell, Dallas, both of Tex. [57] ABSTRACT [73] Assignee: Texas Instruments Incorporated, An MOS/LS1 semiconductor chip for providing the Dallas, e functions of an electronic calculator includes a data memory, an arithmetic unit for executing operations [22] Sept 1973 on data from the memory, and a control arrangement for defining the functioning of the machine including a [21] Appl' 400299 ROM for storing a large number of instruction words, an instruction register for receiving instruction words 52 US. Cl. 340/172.5; 235/153 from the ROM and reading out Parts 10 various 2 tions of the control arrangement, and an address regis- Cl. t t ter for Selecting the ocation in the for e ou Fleld 0f 563mb 146-1 of the next instruction. Input and output terminals are 235/153 AM, 153 153 44/1; 445/1 provided for keyboard input, display output, timing signals, etc. A test mode of operation is provided for References Clled quality control upon completion of manufacture of the chip. The test mode allows the entire ROM to be UNITED STATES PATENTS tested by reading in addresses to the address register from external and reading out the resulting word from 2 5 2/1969 pp 340/1715 the instruction register. During the test mode, normal 52 g:i' incrementing and branching of the address register 3,602,894 8/197l lgel et a] .1 1. 340/17215 may be externally mhlblted' 3,693,162 9/l972 Spangler 340/1725 7 Claims, 59 D i Fi E I 5 5mm!" 5 E3 ARITH'HETIC A]. an '2 LSD 33 :SA 23 T fie s x2%4 :5 LOGIC UNIT an mm B gig Q :1: Apnea, L" LJLJ sumzss 43 1-121:- 1: 2 gg gggggg'j- I I L i a: SHIFT LEFT D-SCAI REG. IG' '7 em 3 am. 0;? {T 4 5 no A am. -"6 35 DBICQAi'T STATE TIMING MATRIX 'L e211. nmn MASK more 35 .,.44 LOGIC our Il cotw. IIIIIIIIIII u 2' :2 c oi rn grrou IZGAICC l 6 [32 R20. -33 n1 n2 n3 M n5 n6 in D8 09 i -31 1 2 a 36 INSTRIIZTIOH REGISTER 37 x ADDRESS ss REG r ADDRESS DECODE\ Y ggg f 46 "no -o- 39 ROM U.S. Patent Nov. 18, 1975 Sheet 1 of 42 3,921,142

US. Patent Nov 18, 1975 Sheet 3 of 42 3,921,142

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STA TES US. Patent Nov. 18, 1975 Sheet 6 of 42 I10 I9 18 17 I6 I5 14 I3 12 11 IO CLASS OPCODE MASK c c o o o 0 o M M M M MSB LSB O J JUMP ADDRESS IF CONDITION RESET 1 JUMP ADDRESS IF CONDITION SET "JUMP ADDRESS IF KEY owN ON Ko(o to 127), o o 1] I JUMP ADDRESS IF KEY DowN ON KP (128 to 255)- [I O 1] FLAS INSTRUcTI0N- MASK [1 l J REGISTER I MASK INS TRUC TI ON US. Patent Nov. 18,1975 Sheet 7 0f 42 3,921,142

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U.S. Patent Nov. 18, 1975 Sheet 8 0142 3,921,142

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US. Patent Nov. 18, 1975 Sheet 18 of 42 3,921,142

US. Patent Nov. 18, 1975 Sheet 19 (M2 3,921,142

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1. A SEMICONDUCTOR CHIP FOR PROVIDING THE FUNCTIONS OF A CALCULATOR, COMPRISING A READ-ONLY-MEMORY FOR STORING A LARGE NUMBER OF INSTRUCTION WORDS, CIRCUIT MEANS CONNECTED TO RECEIVE INSTRUCTION WORDS FROM THE READ-ONLY-MEMORY AND HAVING OUTPUTS, CONTROL MEANS FOR DEFINING THE OPERATION OF THE CALCULATOR, THE CONTROL MEANS HAVING INPUTS CONNECTED TO OUTPUTS OF THE CIRCUIT MEANS, ADDRESS REGISTER MEANS FOR DEFINING A LOCATION IN THE READ-ONLY-MEMORY, CHARACTERIZED IN THAT A TEST MODE OF OPERATION OF THE CALCULATOR IS PROVIDED WHEREIN OPERATION IS DIFFERENT FROM OPERATION IN THE CALCULATE MODE, MEANS CONNECTING ONE OF THE TERMINALS OF THE SEMICONDUCTOR CHIP TO THE ADDRESS REGISTER MEANS TO PERMIT READING IN TO THE ADDRESS REGISTER MEANS A SPECIFIC ADDRESS FROM AN EXTERNAL SOURCE, AND MEANS CONNECTING ANOTHER OF THE TERMINALS OF THE SEMICONDUCTOR CHIP TO SAID CIRCUIT MEANS FOR READING OUT TO EXTERNAL UTILIZATION MEANS AN INSTRUCTION WORD FROM THE READ-ONLY-MEMORY.
 2. A semiconductor chip according to claim 1 wherein a control input is connected to means within the chip for controlling branching to a nonadjacent address in the read-only-memory by loading an address into the address register means from the circuit means.--
 3. In data processing apparatus, a ROM, address register means for defining a location in the ROM, circuit means for receiving instruction words from the ROM, means for incrementing the address register and for branching to a remote location in the ROM using an address defined by the circuit means, and means for reading addresses into the address register from an external source and reading instruction words out to external utilization means via the circuit means while inhibiting said means foR incrementing and branching.--
 4. In data processing appaaratus according to claim 3, data inputs to the apparatus, and means for inhibiting said incrementing and branching by control signals coupled into the apparatus via said data inputs.
 5. In data processing apparatus according to claim 3, the apparatus comprising a semiconductor integrated circuit containing the ROM, address register means and circuit means.
 6. In data processing apparatus according to claim 3, a test control input for disenabling normal operation and enabling a test mode of operation when reading addresses into the address register means.
 7. A semiconductor chip for providing the functions of a calculator, comprising a data memory for storing numerical data, arithmetic means having inputs and outputs selectively connected to the data memory, a read-only-memory for storing a large number of instruction words, address register means for defining a location in the read-only-memory, circuit means connected to receive instruction words from the read-only-memory and having outputs connected to control means for defining the operation of the calculator, a plurality of input/output means for entering numerical data and functional commands into the semiconductor chip as from a keyboard and outputing data as to a display characterized in that means are provided for operation of the semiconductor chip in a test mode of operation, such means including conductor means connecting first of the input/output means to the address register means to permit reading in an address from an external source, and further including conductor means connecting second of the input/output means via the circuit means for reading out an instruction word. 